1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to an input buffer circuit and an output buffer circuit.
2. Description of the Related Art
As illustrated in FIGS. 5 and 6, an input buffer circuit of a conventional semiconductor integrated circuit such as a CMOS (complementary metal-oxide semiconductor) integrated circuit of a complementary insulation gate type comprises pre-buffer PB and main buffer MB each having a CMOS structure. The structure of the pre-buffer varies depending on whether an input signal is at a CMOS level or a TTL (transistor transistor logic) level. Pre-buffer PB of the input buffer circuit shown in FIG. 5 is used to receive an input signal of CMOS level, and pre-buffer PB of the input buffer circuit shown in FIG. 6 is used to receive an input signal of TTL level.
In the pre-buffer PB shown in FIG. 5, the ratio (W/L) of channel width W to channel length of P-channel transistor P1 arranged at the Vcc power source side is 20/1.0, and the ratio of W to L of N-channel transistor N1 arranged at the Vss power source side is also 20/1.0.
In the pre-buffer PB shown in FIG. 6, the ratio of W to L of P-channel transistor P1 is 20/1.0, and the ratio of W to L of N-channel transistor N1 is 80/1.0.
The threshold voltage of a buffer circuit having a CMOS structure depends on the ratio of the driving force of a P-channel transistor to that of an N-channel transistor. When P- and N-channel transistors P1 and N1 of pre-buffer PB in the input buffer circuit shown in FIG. 5, have the same dimension, and the Vcc potential is 5V, the threshold voltage of the circuit is usually 2.5V.
When an input signal is at a TTL level, generally, the low voltage of the input signal is 0.8V and the high voltage is 2.0V. It is thus desirable to set the threshold voltage of a buffer circuit receiving the input signal of TTL level is approximately 1.5V. To set the threshold voltage of a buffer circuit having a CMOS structure in the vicinity of 1.5V, N-channel transistor N1 of pre-buffer PB should have a larger W to L ratio than P-channel transistor Pl, as shown in FIG. 6. For this reason, the dimension ratio of P-channel transistor P1 to N-channel transistor N1 is one to four.
FIG. 7 is a graph showing the input/output voltage transmission characteristics of pre-buffers PB of the input buffer circuits illustrated in FIGS. 5 and 6. Assume that input voltage increases from 0V to 5V. In pre-buffer PB shown in FIG. 5, an output voltage decreases from 5V to 0V when the input voltage reaches 2.5V, and the threshold voltage of the input buffer circuit is 2.5V. In pre-buffer PB shown in FIG. 6, the output voltage decreases from 5V to 0V when the input voltage reaches around 1.5V, and it turns out that the threshold voltage of the input buffer circuit changes with the ratio of the driving force of P-channel transistor P1 to that of N-channel transistor N1.
In the input buffer circuit shown in FIG. 6, when the threshold voltage of pre-buffer PB is set in the vicinity of 1.5V to receive an input signal of TTL level, a semiconductor integrated circuit having a pattern is designed by the full-custom specification (completely custom-made pattern) can be miniaturized as far as a design rule allows. However, the dimension of a conventional semiconductor integrated circuit such as a gate array in which the sizes of transistors are predetermined, inevitably becomes larger at its N-channel transistor side, and, accordingly the pattern area is greatly enlarged.
The conventional semiconductor integrated circuit has the following problems.
(a) When a desired low value (e.g., 1.5V) is required as a threshold voltage to realize an input buffer circuit applicable to receiving an input signal of TTL level, the dimension of the circuit becomes large at the N-channel transistor side, and thus the pattern area is greatly enlarged. Therefore, a large amount of peak current is caused by the switching operation of the buffer circuit, and the amount of instantaneous current per time becomes very large.
(b) When the threshold voltage has a low value such as 1.5V, it is necessary to cause the dimensions of the P- and N-channel transistors to greatly differ from each other. The balance between the rise and fall of a signal is greatly deteriorated.
(c) When an input buffer circuit applicable to receiving an input signal of TTL level is realized, in a stationary state where a voltage of 3V is input to pre-buffer PB, not only N-channel transistor N1 of prebuffer PB, but also P-channel transistor P1 is turned on because the source-to-gate voltage of P-channel transistor P1 is 2V. Therefore, a through current in the order of several hundreds of microamperes per pre-buffer flows.
(d) When a plurality of buffer circuits connected in common to a power source line is switched at the same time, and the N-channel transistor of each of the buffer circuits is very large in dimension, a large amount of peak current is caused by the switching operation of the buffer circuits, and the amount of instantaneous current per unit of time (di/dt) becomes large. For this reason, the power source line cannot be kept at a constant voltage, and the level of the output signal of each buffer circuit is very high, thereby causing great ringing which results in malfunction of the circuit. This problem will be described in detail with reference to FIGS. 8 and 9.
FIG. 8 is a schematic view showing an input buffer circuit group (or an output buffer circuit group) in a conventional large scale semiconductor integrated circuit. Usually, buffer circuits 81i (i=1, 2, . . . , n) of the input buffer circuit group (or output buffer circuit group) are connected in common to the power source lines (Vcc power source lines and Vss power source lines).
FIG. 9 is a graph showing input/output characteristics in a case where n buffer circuits 81i of the input buffer circuit group (or output buffer circuit group) shown in FIG. 8 are simultaneously switched. When input signals INi of n buffer circuits 81i rise at the same time, output signals INmi of the pre-buffers of n buffer circuits 81i fall at the same time. If the N-channel transistor of each of the pre-buffers is very large, the amount of instantaneous current per unit of time (di/dt) caused by the switching operation of the buffer circuits becomes very large. Since the pre-buffers of n buffer circuits 81i are simultaneously switched, the levels of the power source lines cannot be kept constant, and thus great ringing occurs in output signal INmi of each prebuffer at a ground potential level.
Furthermore, great ringing occurs in output signal OUTi of each of the main buffers receiving output signal INmi, at a power source potential level. If the amplitude of the ringing of output signal INmi or OUTi exceeds 2.5V, the circuit will malfunction. Since n buffer circuits 81i are simultaneously switched, noise is generated in the power source lines, and any other circuits having common power source lines will also malfunction. Recently, a data length used in a system such as a microcomputer has been changed from 8 bits to 16 bits and then from 16 bits to 32 bits, and the buffer circuits of an input buffer circuit group or an output buffer circuit group of a semiconductor integrated circuit used in such a system tends to increase in number. The operation speed of the system becomes high, and, if the amplitude of the ringing of an output signal of the buffer circuit is large, as described above, it is almost impossible to detect whether data is "1" or "0".